It is known to make use of a circuit that outputs a pulse-width-modulated signal as a digital-to-analog converter (D/A converter). The circuit outputs a pulse-width-modulated signal having a width conforming to the digital value of a digital signal. An overview of a D/A converter of this type will be described with reference to the teachings of Patent Document 1. FIGS. 13 to 15 are excerpted from Patent Document 1. With reference to FIG. 13, the output digital signal of a ΔΣ modulating circuit 4 is supplied to a pulse-width modulation (PWM) circuit 5 constituting a D/A converter. The PWM circuit 5 outputs a pulse-width-modulated signal having pulse widths the number which conforms to the number of bits of the digital signal input thereto. For example, if the input digital signal has three bits, the PWM circuit 5 outputs a pulse-width-modulated signal having seven types of pulse widths conforming to the digital value.
A distortion correction component generating circuit 3 generates a component Dn, which is for correcting harmonic distortion produced in the PWM circuit 5, from the input signal. A phase correcting circuit 10 outputs a signal Dc, which is obtained by applying a phase correction to the input signal, in such a manner that the signal Dc will be exactly opposite in phase to the distortion correction component Dn generated by the distortion correction component generating circuit 3. A subtractor 2 subtracts Dd from Dc, thereby diminishing beforehand a component corresponding to distortion produced in the PWM circuit 5.
The distortion correction component generating circuit 3 is adapted to artificially generate the harmonic component of the input signal by computation. The phase correcting circuit 10 has a characteristic that is opposite in phase to that of the signal produced by the distortion correction component generating circuit 3.
FIG. 14 illustrates an example of configurations of the phase correcting circuit 10 and distortion correction component generating circuit 3 in a case where second-order harmonic distortion of a reproduced signal generated by the PWM circuit 5 is removed (see FIG. 2 in Patent Document 1). Specifically, in this example, the phase correcting circuit 10 has a delay circuit 11 for applying a delay commensurate with one sample of an input digital audio signal Di. The phase correcting circuit 10 has a transfer function Ha, given as follows:Ha=Z−1,where Z−1 represents delay of one sample by a Z function. The distortion correction component generating circuit 3 has a multiplier 31, an amplifier 32, one-sample delay circuits 33 and 35 and subtractor circuits 34 and 36. The distortion correction component generating circuit 3 has a transfer function He, which can be written as follows:He=α·x2·(1−Z−1)2 where α is a constant, x is the value of the input digital signal and Z−1 represents delay of one sample by a Z function.
Harmonic distortion of a reproduced signal component is produced in the PWM circuit 5, with second-order harmonic distortion being the largest. Even when the normalized frequency is high, the arrangement shown in FIG. 13 is capable of sufficiently suppressing second-harmonic distortion produced in the PWM circuit 5 from the reproduced signal component.
FIG. 15 illustrates an example of the configuration of a D/A converter for removing a plurality of harmonic distortions (see FIG. 8 in Patent Document 1). The distortion correction component generating circuit 3 has distortion correction component generators 301, 302, . . . and 30m for generating distortion correction components corresponding to m-number (where m is an integer equal to or greater than 2) of n-order harmonic distortions such as second-order distortion, third-order distortion, and so on. The distortion correction component generators 301, 302, . . . and 30m have respective ones of transfer functions He1, He2, . . . and Hem for generating distortion correction components Dn1, Dn2, . . . and Dnm for removing, from a digital signal Di from an input terminal 1, harmonic distortions of corresponding orders among m-number of orders of harmonics produced in the PWM circuit 5. The distortion correction components Dn1, Dn2, . . . and Dnm from the distortion correction component generators 301, 302, . . . and 30m are supplied to an adder circuit 310. The adder circuit 310 generates a distortion correction component Dn as the output of the sum of the m-number of distortion correction components Dn1, Dn2, . . . and Dnm, and supplies the distortion correction component Dn to the subtractor circuit 2, which subtracts Dn from the digital signal from phase correcting circuit 10. The phase correcting circuit 10 has phase correction units 101, 102, . . . and 10m for correcting the phase characteristics of the input digital signal Di so as to conform to the phase characteristics of the m-number of distortion correction component generators 301, 302, . . . and 30m. The phase correction units 101, 102, . . . and 10m have respective ones of transfer functions Ha1, Ha2, . . . and Ham for correcting the phase of the input digital signal Di in such a manner that, irrespective of the normalized frequency, the m-number of n-order harmonic distortions produced in the PWM circuit 5 with regard to the input digital signal Di will be opposite in phase in PWM circuit 5 with respect to distortion correction components Dn1, Dn2, . . . and Dnm obtained through the subtractor circuit 2. Phase-corrected digital signals Dc1, Dc2, . . . Dcn from the phase correction units 101, 102, . . . and 10m are supplied to an adder circuit 310. The adder circuit 310 generates a digital signal Dc, the amplitude and phase of which have been corrected, as the output of the sum of the m-number of digital signals Dc1, Dc2, . . . and Dcn, and supplies the digital signal Dc to the subtractor circuit 2, thereby removing a plurality of n-order harmonic distortions.
[Patent Document 1]
JP Patent No. 3772970 (Japanese Patent Kokai Publication No. JP-P2003-133959A)